• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In a conventional memory subsystem, a memory controller issues explicit update commands to a DRAM memory device to maintain the integrity of the data stored on the memory device when the memory device is in automatic update mode. A significant amount of energy can be consumed to perform the upgrade. To solve this and other problems, it is proposed to allow a partial update in the automatic update mode, in which the update operation can be ignored for a subset of the memory cells. With this selective update leap, the energy consumed for automatic updates can be reduced. Operating system kernels and memory drivers can be configured to determine areas of memory for which the update operation can be bypassed.
    公开号:BR112020001854A2
    申请号:R112020001854-6
    申请日:2018-05-25
    公开日:2020-07-28
    发明作者:Jungwon Suh；Yanru Li；Michael Hawjing Lo；Dexter Tamio Chun
    申请人:Qualcomm Incorporated；
    IPC主号:
    专利说明:

    [0001] [0001] The subject field disclosed refers to memory devices. In particular, the disclosed subject field refers to partial update operations on memory devices to save energy. Foundations
    [0002] [0002] Memory devices, such as DRAM (Dynamic Random Access Memory), are widely used in computing devices, including mobile devices, to store data. To maintain data integrity, DRAMS cells are updated periodically. As the density and speed of DRAMs increases, the impact of update operations on DRAM's overall performance and energy consumption becomes increasingly non-trivial. The impact of the update operation can be particularly significant on mobile devices, as power consumption is a major concern on these devices. SUMMARY
    [0003] [0003] This summary identifies features of some aspects of the example and is not an exclusive or exhaustive description of the matter disclosed. Whether resources or aspects are included or omitted in this Summary is not intended to be indicative of the relative importance of such resources. Additional features and features are described and will become apparent to those skilled in the art by reading the detailed description below and viewing the drawings that are part of it.
    [0004] [0004] An exemplary device is released. The apparatus may comprise a memory device and the memory device may comprise a plurality of memory cells and a partial array update mask register. When the memory device is in automatic update mode and automatic partial matrix update is enabled, a portion of the plurality of memory cells can be masked from being updated based on the partial matrix update mask register.
    [0005] [0005] An exemplary device is released. The device may comprise a system on the chip and a memory device configured to communicate with each other over a link. The system on the chip can be configured to provide commands to the memory device via the link. The memory device can be configured to be in auto update mode or auto update mode. The memory device can comprise a plurality of memory cells. The memory device may also comprise a partial array update mask register. When the memory device is in auto update mode and a partial matrix auto update is enabled, the memory device can update a subset of the selected memory cells according to the partial matrix update mask register without receiving commands. system update on the chip. When the memory device is in automatic update mode and an automatic partial matrix update is enabled, the memory device can update the subset of the selected memory cells according to the partial matrix update mask register upon receiving the command system update on the chip.
    [0006] [0006] An exemplary method for reducing energy consumption in a computer system device is disclosed. The device may comprise a system on the chip and a memory device configured to communicate with each other over a link. The system on the chip can be configured to provide commands to the memory device via the link. The memory device can comprise a plurality of memory cells. The memory device may also comprise a plurality of mode registers configured to implement a partial matrix update enable register and a partial matrix update mask register. The partial matrix update enable register may comprise a plurality of enable bits, including a partial matrix auto update enable bit and a partial matrix automatic update enable bit. The partial matrix auto update enable bit when set may indicate that the partial matrix auto update is enabled and the partial matrix automatic update enable bit when set may indicate that automatic partial matrix update is enabled. In the method, the system on the chip can issue, for each mode register used to implement the partial matrix update enable register, a mode register write command with a mode value corresponding to the memory device to set the bit partial matrix update enable registry from the partial matrix update enable registry. The system on the chip can also issue, for each mode register used to implement the partial matrix update mask register, the mode register write command with the mode value corresponding to the memory device, to make a mask value is written to the partial array update mask register where the mask value corresponds to the ignored update region. The system on the chip can issue an update command to the memory device. If the partial matrix automatic update enable bit is set when the update command is issued, the memory device can bypass the update of the ignored update region based on the partial matrix update mask register.
    [0007] [0007] An exemplary device is released. The device may comprise a system on the chip and a memory device configured to communicate with each other over a link. The system on the chip can be configured to provide commands to the memory device via the link. The memory device can be configured to be in auto update mode or auto update mode. The memory device may comprise and a plurality of memory cells, a partial array update mask register and means for updating. When the memory device is in auto update mode and a partial matrix auto update is enabled, the means for updating can update a subset of the selected memory cells according to the partial matrix update mask register without receiving commands. system update on the chip. When the memory device is in automatic update mode and an automatic partial matrix update is enabled, the means for updating can update the subset of the selected memory cells according to the partial matrix update mask register upon receiving the command system update on the chip. BRIEF DESCRIPTION OF THE DRAWINGS
    [0008] [0008] The accompanying drawings are presented to assist in the description of examples of one or more aspects of the disclosed subject and are provided only for illustration of the examples and not for limiting them:
    [0009] [0009] FIG. 1 illustrates an example of a memory subsystem;
    [0010] [0010] FIG. 2 illustrates an example of a memory device;
    [0011] [0011] FIG. 3 illustrates an example of partitioning a plurality of memory cells from a memory device;
    [0012] [0012] FIG. 4 illustrates an example of a mode register used to implement a partial matrix update enable register;
    [0013] [0013] FIGS. 5A and 5B illustrate examples of mode registers used to implement a partial matrix mask;
    [0014] [0014] FIGS. 6A - 6D illustrate different scenarios in which update operations are performed and ignored based on masking when an update command for all banks is issued when automatic update of the partial matrix is enabled;
    [0015] [0015] FIGS. 7A and 7B illustrate different scenarios in which update operations are performed and ignored based on masking when a partial bank update command is issued when automatic matrix update is enabled;
    [0016] [0016] FIGS. 8A and 8B, respectively, illustrate the hierarchical and hardware arrangement of an example computing system;
    [0017] [0017] FIG. 9 illustrates an example of runtime interaction between components of a computing system; and
    [0018] [0018] FIG. 10 illustrates examples of devices with a memory subsystem integrated into it. DETAILED DESCRIPTION
    [0019] [0019] Aspects of the subject are provided in the following description and related drawings directed to specific examples of the disclosed subject. Substitutes may be created without departing from the scope of the matter disclosed. In addition, known elements will not be described in detail or will be omitted in order not to hide relevant details.
    [0020] [0020] The word "exemplary" is used here to mean "serving as an example, instance or illustration". Any modality described here as "exemplary" should not necessarily be interpreted as preferred or advantageous over other modalities. Likewise, the term "modalities" does not require that all modalities of the disclosed object include the resource, advantage or mode of operation discussed.
    [0021] [0021] The terminology used in this document is intended to describe only particular examples and is not intended to be limiting. As used here, the singular forms "one", "one" and "o / a" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "includes" and / or "including", when used here, specify the presence of declared resources, integers, processes, operations, elements and / or components, but not excludes the presence or addition of one or more resources, whole numbers, processes, operations, elements, components and / or groups thereof.
    [0022] [0022] In addition, many examples are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that several actions described in this document can be performed by specific circuits (for example, application-specific integrated circuits (ASICs)), by program instructions being executed by one or more processors, or by a combination of both. In addition, this sequence of actions described here can be considered to be incorporated entirely into any form of computer-readable storage medium, having stored in it a corresponding set of computer instructions that, after execution, would take an associated processor to perform the functionality. described here. Thus, the various aspects can be incorporated in several different forms, all of which were considered to be within the scope of the claimed object. In addition, for each of the examples described here, the corresponding form of any of these examples can be described here as, for example, "logic configured to" perform the described action.
    [0023] [0023] A DRAM cell usually includes an access transistor and a capacitor. The data is stored as an electrical charge in the capacitor. Over time, the charge on the capacitor leaks. To retain the data in the leaking capacitor, periodic updates that consume energy are performed. On mobile devices, the energy consumed to perform updates can be a significant concern.
    [0024] [0024] DRAM devices, including mobile DRAM devices, generally support two methods - auto update (SR) and automatic update (AR). The SR is used when the DRAM device is in an idle or low power state. In the JEDEC (Joint Electron Device Engineering Council) standard document LPDDR4 (Low Power Dual Data Rate 4) JESD209-4A, which is incorporated by reference in its entirety, a DRAM device enters and exits SR mode when receiving input commands auto update (SRE) and auto update output (SRX) commands from a memory controller. The DRAM device includes an internal timer that allows to accommodate the auto update operation. When in SR mode, the SDRAM device can retain data without receiving an update command from the memory controller.
    [0025] [0025] To reduce the auto update current ("IDD6" in JEDEC) and therefore reduce the energy consumed for auto update, a mobile DRAM device provides a partial matrix auto update (PASR) function that performs an update of partial array (PAR) during SR mode. In PASR, the memory controller programs the mobile DRAM device to update only a portion of the memory via a PASR mask.
    [0026] [0026] When the DRAM device is in an active state, automatic update is used to retain data in the DRAM cell. In AR mode, the memory controller provides an explicit update REF command to the mobile DRAM device. To reduce the automatic update current ("IDD5" in JEDEC), existing solutions focus on controlling the automatic update rate tREFI based on temperature. As an illustration, as the temperature of the device decreases, the automatic refresh rate may also decrease, for example, to half the normal refresh rate or 2 * tREFI. In effect, the overall consumption of IDD5 is reduced in conventional solutions, extending the time between updates, for example, decreasing the emission rate of REF commands.
    [0027] [0027] However, in a non-limiting aspect, it is proposed to allow partial matrix updates, even when the memory device is in the active state. In other words, an automatic partial matrix update (PAAR) can be enabled, in which the update is ignored for some memory cells during the update operation. In this way, the automatic update current can be reduced.
    [0028] [0028] An example of a memory subsystem is illustrated in FIG. 1. The memory subsystem 100 can include a system on the chip (SOC) 110 and one or more memory devices 120 communicating over a link 130. In reality, link 130 can comprise a plurality of signal lines, including lines to transmit unidirectional signals from SOC 110 to memory devices 120 (for example, clock (CK), chip selection (CS), command and address (CA), etc.) and bidirectional directional signals (data (DQ), strobe) (DQS), etc.).
    [0029] [0029] SOC 110 may include a memory controller 115 and a PHY 117 block. SOC 110 and memory devices 120 may be in communication with each other via link 130. In particular, memory controller 115 may control the memory devices 120 exchanging signals to write data and read data from memory cells of memory devices 120.
    [0030] [0030] As seen in the figure, there can be N memory devices 120-1 ... 120-N, where N can be any integer greater than zero. An example of a memory device 120 is illustrated in FIG. 2. As seen, memory device 120 may include an input / output (I / O) circuit 210 configured to interact with memory controller 115. I / O circuit 210 may be an example of an interface medium. Memory controller 115 can be considered external to memory device 120. I / O circuit 210 can also be configured to write and read data from a plurality of memory cells. The memory cells of the memory device 120 can be DRAM cells that store data as charges in the capacitors.
    [0031] [0031] In one aspect, the plurality of memory cells can be partitioned into a plurality of memory banks 220 or simply banks 220. As seen, there may be P banks 220-1 ... 220-P, where P can be any integer greater than zero. The memory cells in each bank 220 can further be partitioned into a plurality of blocks or segments. Note that memory cells in a bank can be segmented in several ways, including row addresses, column addresses or a combination of them. FIG. 3 illustrates an example of partitioning the plurality of memory cells of memory device 120. In this figure, it is assumed that there are eight banks, that is, P = 8. In addition, within each bank, it is assumed that there are eight segments per bank. Obviously, this is just an example and is not a limitation.
    [0032] [0032] Returning to FIG. 2, the memory device 120 may further include a plurality of mode registers (MR) 230. The mode registers 230 may define the behavior of the memory device
    [0033] [0033] When the memory cells of the memory device 120 are DRAM cells, periodic updates are carried out to maintain the integrity of the data stored in the cells. Memory device 120 can be configured to be in auto update (SR) mode or automatic update (AR) mode. In one aspect, memory device 120 can enter and exit SR mode by receiving, respectively, the auto update input (SRE) and auto update output (SRX) commands from memory controller 115.
    [0034] [0034] As indicated, when memory device 120 is in SR mode, memory device 120 (for example, I / O circuit 210 or some other component) can be configured to update memory cells without receiving commands update (REF) of memory controller 115. In this mode, memory device 120 can generate the necessary update pulses via an internal timer (not shown) and thus negate the need for memory controller 115 to issue REF commands explicit. SR mode can be considered as a low energy update mode, as SOC 110 can be placed in an idle state to reduce energy consumption.
    [0035] [0035] On the other hand, when the memory device 120 is in the active state, that is, when it is in the AR mode, the memory controller 115 can control the update operation by issuing REF commands. I / O circuit 210 can be configured to update memory cells upon receiving the REF command from memory controller 115. To reduce the consumption of the automatic update current (for example, IDD5), it is proposed to enable the memory 120 to update a subset - less than all - of the memory cells when memory controller 115 issues the REF command. That is, it is proposed to allow partial update of the matrix in which the update operation is ignored for a non-zero number of memory cells.
    [0036] [0036] Masking can be used to specify the portions of the memory cells for which update operations are to be ignored and other portions for which update operations are to be performed. To enable update masking, memory device 120 may include a partial array update enable register and a partial array update mask register. The bits of the PAR enable register can indicate whether one, both, or no automatic update of the partial matrix (PAAR) and auto update of the partial matrix (PAAR) are enabled. A mask value in the PAR mask register can indicate the portions of the memory cells in which the update operations are to be ignored, as well as the portions in which the update operations are to be performed.
    [0037] [0037] The PAR enabling register can comprise a plurality of enabling bits, including a PAAR enabling bit and a PASR enabling bit. The PAAR enable bit, when set or not, can indicate that PAAR is enabled or disabled. Likewise, the PASR enable bit, when set or not, can indicate that PASR is enabled or disabled. One or more of the 230 mode registers can be used to implement the PAR enabling register. For each mode register 230 used to implement the PAR enable register, memory controller 115 can issue an MRW command along with a corresponding mode value. The I / O circuit 210, in turn, can write the corresponding mode value in this mode register 230. In this way, the PAAR enable bit can be set or disabled and the PASR enable bit can be set or disabled.
    [0038] [0038] FIG. 4 illustrates an example of a 230 mode register used to implement the PAR enable register. In this example, it is assumed that the mode register 230 for the enabling enable PAR comprises eight operating bits (OP) in which the bits OP [1] and OP [0] are respectively the enable bit PAAR and the enable bit PASR. The PAAR enable bit, when set or not, indicates that PAAR is enabled or disabled. Likewise, the PASR enable bit, when set or not, indicates that PASR is enabled or disabled. The value represented by the OP bits [1: 0] of the PAR enable register can be called the update enable value.
    [0039] [0039] One or more different 230 mode registers can be used to implement the PAR mask register. The PAR mask register may include a plurality of segment mask bits, a plurality of bank mask bits, or both. For each mode register 230 used to implement the PAR mask register, memory controller 115 can issue an MRW command along with a corresponding mode value. In turn, I / O circuit 210 can write the corresponding mode value to this 230 mode register. In this way, the mask value can be written to the PAR mask register.
    [0040] [0040] FIGS. 5A and 5B illustrate examples of the 230 mode registers used to implement the PAR mask register. In this example, the assumption is that the memory cells are partitioned into eight banks and eight segments per bank, as illustrated in FIG. 3. Therefore, in this case, the PAR mask register can include the segment mask bits and the bank mask bits. The eight segment mask bits can be implemented using one of the 230 mode registers, as illustrated in FIG. 5A. Each OP bit in FIG. 5A can correspond to a segment of a bank and can indicate whether the update is enabled or disabled for the corresponding segment. The eight bank mask bits can be implemented using another 230 mode register, as illustrated in FIG. 5B. Each OP bit in FIG. 5B can correspond to a bank and can indicate whether updating is enabled or disabled for the corresponding bank.
    [0041] [0041] Obviously, this is just an example and should not be taken as limiting. If the memory cells are partitioned only into segments or only into banks, a single 230 mode register may be sufficient to implement the PAR mask register. If memory cells are partitioned in other ways, more 230 mode registers may be required for the implementation of the PAR mask register.
    [0042] [0042] Returning to FIGs. 5A and 5B, when memory device 120 is in AR mode and PAAR is enabled (i.e., the PAR enable register's PAAR enable bit is set), memory device 120 can update a subset of cells selected according to the PAR mask register when receiving the REF command from memory controller 115. The REF command can be an update command for all banks (REFab) or an update command per bank (REFpb). Different update operations can be loaded depending on the type of the REF command (REFab or REFpb) and whether the PAR mask includes the segment and / or bank mask bits.
    [0043] [0043] In the first to four scenarios illustrated in FIGs. 6A to 6D, it can be assumed that memory device 120 is in AR mode, PAAR is enabled and the REF command is the REFab command for updating all banks. In addition, if segment masking is applied, assume that the segment mask bits indicate that updating is disabled for segments 4 and 6. In addition, if bank masking is applied, assume that the mask bits of the indicate that the update is disabled for banks 3, 5 and
    [0044] [0044] In the first scenario, it can be assumed that only segment masking is applied. This may be because the PAAR mask register includes only the segment mask bits or bank masking is disabled. In this first scenario, memory device 120 may, for each bank, ignore the update of each segment whose corresponding segment mask bit indicates that the update is disabled for that segment. An example is illustrated in FIG. 6A where the shaded segments represent the segments for which the update was ignored. Note that segments 4 and 6 for all eight banks are shaded.
    [0045] [0045] In the second scenario, it can be assumed that only bank masking is applied. This may be because the PAAR mask register includes only the bank mask bits or segment masking is disabled. In the second scenario, the memory device 120 may, for each bank, ignore the update of that bank when the mask bit of the corresponding bank indicates that the update is disabled for that bank. An example is illustrated in FIG. 6B where all bank segments 3, 5 and 6 are shaded.
    [0046] [0046] In the third scenario, it can be assumed that bank and segment masking is applied. In the third scenario, the update operation can be ignored for a bank segment when the bank mask bits and corresponding segments indicate that the update is disabled. An example is illustrated in FIG. 6C. Note that if the update is ignored for a segment only when the bank and segment mask bits indicate that the update is disabled, the first scenario in FIG. 6A can be recreated by enabling all bank mask bits while disabling the segment mask bits of segments 4 and 6, and the second scenario of FIG. 6B can be recreated by enabling all segment mask bits while disabling bank mask bits from banks 3, 5 and 6.
    [0047] [0047] In the fourth scenario, it can also be assumed that bank and segment masking is applied. However, in the fourth scenario, the update operation can be ignored for a bank segment when the corresponding bank mask bit or the corresponding segment mask bit indicates that the update is disabled. An example is illustrated in FIG. 6D. Note that if the update is ignored for a bank segment when one of its bank bits or segment mask indicates that the update is disabled, the first scenario in FIG. 6A can be recreated by disabling all bank mask bits while disabling the segment mask bits of segments 4 and 6 and the second scenario of FIG. 6B can be recreated by disabling all segment mask bits and disabling bank mask bits from banks 3, 5 and 6.
    [0048] [0048] In the fifth and sixth scenarios illustrated in FIGs. 7A to 7B, it can be assumed that memory device 120 is in AR mode, PAAR is enabled and the REF command is the REFpb command for updating by bank (as opposed to the REFab command in the scenarios of FIGS. 6A to 6D) . If segment masking is applied, suppose that the segment mask bits indicate that the update is disabled for segments 4 and 6. If bank masking is applied, assume that the bank mask bits indicate that the update is disabled for banks 3, 5 and 6. Also, assume that bank 3 is the current bank to which the REFpb command applies.
    [0049] [0049] In the fifth scenario, like the first, it can be assumed that only segment masking is applied. In this fifth scenario, memory device 120 may ignore the update of each segment of the current bank - bank 3 - whose corresponding segment mask bit indicates that the update is disabled. An example is illustrated in FIG. 7A. As seen, the update operations for segments 4 and 6 of bank 3 are ignored. When only segment masking is applied, running through eight REFpb commands, results similar to FIG. 6A can be achieved.
    [0050] [0050] In the sixth scenario, as in the second scenario, it can be assumed that only bank masking is applied. In the sixth scenario, memory device 120 may ignore the update of the current bank in its entirety if the mask bit of the corresponding bank indicates that the update is disabled. An example is illustrated in FIG. 7B. As seen, update operations are ignored for all segments of bank 3. When only bank masking is applied, running through eight REFpb commands, results similar to FIG. 6B can be achieved.
    [0051] [0051] Although not specifically illustrated, the bank and segment mask bits can be applied to the REFpb command. In a scenario, assume that the update is ignored for a bank segment only when the bank and segment mask bits indicate that the update is disabled. In this scenario, segment masking can be applied to bypass the update of selected segments (for example, segments 4 and 6) if the update is disabled for the current bank (for example, bank 3). On the other hand, if the update is enabled for the current bank, the entire current bank can be updated regardless of the segment mask, that is, no update jump for any current bank segment (not shown). In this case, running through eight REFpb commands, results similar to FIG. 6C can be achieved.
    [0052] [0052] In another scenario, suppose that the update is ignored for a bank segment when its bank or segment mask bit indicates that the update is disabled. In this scenario, segment masking can be applied to bypass the update of selected segments (for example, segments 4 and 6), regardless of whether the update is enabled or disabled for the current bank (for example, bank 3). In this case, running through eight REFpb commands, results similar to FIG. 6D can be achieved.
    [0053] [0053] In one aspect, the same PAR mask register, that is, the same or more mode registers
    [0054] [0054] The memory controller 115 can issue MRW commands to the PAR enable register, and I / O circuit 210 can write the update enable value to the PAR enable register to set the PASR enable bit. The memory controller 115 can also issue MRW commands to the PAR mask register and I / O circuit 210 can write the mask value to the PAR mask register. The memory controller 115 can issue the MRW command (s) before commanding the mobile device 120 to enter SR mode.
    [0055] [0055] While in SR mode, if the PAR mask register includes only segment mask bits or bank masking is disabled, memory device 120 can, for each bank, ignore the update of each segment whose bit of The corresponding segment mask indicates that the update is disabled for that segment. This is similar to the first scenario illustrated in FIG. 6A. If the PAR mask register includes only the bank mask bits or segment masking is disabled, memory device 120 may, for each bank, ignore the update of that bank when the corresponding bank mask bit indicates that the update is disabled for that bank. This is similar to the second scenario illustrated in FIG. 6B.
    [0056] [0056] If the PAR mask register includes the bank and mask bits, memory device 120 can ignore update operations for a bank segment when the bank mask bits and corresponding segments indicate that the update is disabled. This is similar to the third scenario illustrated in FIG. 6C. Alternatively, the update operation can be ignored for a bank segment when the corresponding bank mask bit or the corresponding segment mask bit indicates that the update is disabled. This is similar to the third scenario illustrated in FIG. 6D.
    [0057] [0057] FIG. 8A illustrates an example block diagram of a computing system 800 that can include a processor 810 and a memory subsystem 100. For the sake of simplicity, other components, such as input devices (eg keyboards, touch pads), output devices (eg monitors) and non-volatile storage (eg flash, disks) are not shown in FIG. 8A. In addition, the computing system 800 may include one or more processing units (e.g., CPUs), which are represented collectively by the processor 810. The memory subsystem 100 has been described in detail above. As seen, processor 810 and memory subsystem 100 can communicate with each other.
    [0058] [0058] FIG. 8A illustrates an example of a hardware composition of computing system 800. FIG. 8B illustrates an example of a hierarchical arrangement of the same computing system 800. The computing system 800 can comprise an 815 application, a high-level operating system (HLOS) kernel 825, a memory driver 835, the memory controller 115 and memory device 120, which can be arranged hierarchically in which application 815 is at the top and memory device 120 is at the bottom of the hierarchy. Remember that there may be several memory devices 120 controlled by memory controller 115. But, for simplicity of description, a memory device 120 is shown.
    [0059] [0059] The memory controller 115 and the memory device 120 can be largely or even exclusively hardware. The 815 application, the HLOS 825 kernel and the 835 memory driver can be a combination of hardware and software. For example, the 810 processor can execute instructions from the 815 application, the HLOS 825 kernel and the 835 memory driver. As seen in FIG. 8, memory controller 115 may be in communication with memory driver 835.
    [0060] [0060] In one aspect, it is proposed that the top-level components - the 815 application, the HLOS kernel and the 835 memory driver - use the PAAR feature of memory devices 120 to save energy consumption. At startup, memory driver 835 can save attributes of memory device 120 in a RAM partition table in which all memory cells of memory device 120 are divided into regions. The RAM partition can be readable. The HLOS kernel can generate a memory topology, including power attributes, performance attributes, and physical group addresses based on the RAM partition.
    [0061] [0061] A user interface can be provided to allow a user of the 800 computing system to configure the conditions under which an energy saving mode is triggered. For example, the power saving mode can be triggered based on the battery limit level. Alternatively or in addition, the energy saving mode can be activated when the computer system is in low activity for a limited time period. Various limits can be set for different levels of active energy savings.
    [0062] [0062] FIG. 9 illustrates an example of runtime interaction between components of the computing system 800. In block 910, an application 815, as a system event handler, can detect an event and invoke a callback to the HLOS 825 kernel For example, a user may have exited a user application running on the 800 computer system and the user application's data may have been saved in non-volatile storage. In this instance, user application data does not need to be kept on memory device 120. At block 920, the HLOS 825 kernel can free a memory region of user application data and notify memory driver 835 of the memory region released.
    [0063] [0063] In block 930, memory driver 835 can convert the released memory region into an ignored update region, in which the ignored update region comprises one or more portions of the memory cells of memory device 120 that do not require update. In block 940, memory driver 835 can provide information about the ignored update region for memory controller 115. In block 945, memory controller 115 can respond by issuing MRW commands to memory device 120 to set the bit PAAR enabling register of the PAR enabling register and writing a mask value corresponding to the ignored update region in the PAR mask register.
    [0064] [0064] In block 950, memory driver 835 can instruct memory controller 115 to adjust an update interval, for example, tREFI, based on the region of memory released. For example, when the update is ignored for a non-zero portion of the memory cells, less energy is consumed and the memory device 120 can run cooler. Therefore, it may be safe to decrease the refresh rate. In block 955, memory controller 115 can respond by waiting at least the adjusted update interval after issuing a REF command and before issuing another REF command to memory device 120.
    [0065] [0065] FIG. 10 illustrates various electronic devices that can be integrated into any of the memory subsystems 100 mentioned above. For example, a mobile phone device 1002, a laptop device 1004, a terminal device 1006, as well as wearable devices, portable systems, which require a small form factor, extremely low profile, may include a device / package 1000 that incorporates the memory subsystem 100 as described herein.
    [0066] [0066] Those skilled in the art will appreciate that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles or any combination of the same.
    [0067] [0067] In addition, those skilled in the art will understand that the various logic blocks, modules, circuits and illustrative algorithms described in connection with the examples disclosed herein can be implemented as electronic hardware, computer software or combinations of both. To clearly illustrate this interchangeability of hardware and software, several components, blocks, modules, circuits and illustrative methods have been described above generally in terms of functionality. Whether this functionality is implemented as hardware or software depends on the specific application and design restrictions imposed on the general system. Qualified experts can implement the functionality described in a number of ways for each particular application, but these implementation decisions should not be interpreted as causing a departure from the scope of this disclosure.
    [0068] [0068] The methods, sequences and / or algorithms described in connection with the examples disclosed here can be incorporated directly into the hardware, in a software module executed by a processor or in a combination of the two. A software module can reside in RAM, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM or any other form of storage known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor.
    [0069] [0069] Therefore, an aspect may include a computer-readable medium that incorporates a method to form a semiconductor device. Therefore, the scope of the disclosed object is not limited to illustrated examples and any means to carry out the functionality described here is included.
    [0070] [0070] Although the previous disclosure shows illustrative examples, it should be noted that various changes and modifications can be made here without departing from the scope of the disclosed object, as defined by the attached claims. The functions, processes and / or actions of the method claims according to the examples described here need not be performed in any specific order. In addition, although elements of the disclosed object may be described or claimed in the singular, the plural is contemplated, unless the limitation to the singular is explicitly stated.
    权利要求:
    Claims (26)
    [1]
    1. An apparatus, comprising: a memory device, comprising: a plurality of memory cells; and a partial array update mask (PAR) register, where when the memory device is in automatic update mode and when an automatic partial matrix update (PAAR) is enabled, a portion of the plurality of memory cells is masked to be updated based on the PAR mask register.
    [2]
    Apparatus according to claim 1, further comprising a system on the chip (SOC) configured to provide commands to the memory device via a link.
    [3]
    Apparatus according to claim 2, wherein the apparatus is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a navigation device communication, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop, a server and a device in an automotive vehicle.
    [4]
    Apparatus according to claim 2, wherein the PAR mask register is configured to mask the portion of the plurality of memory cells in automatic update mode and an auto update mode.
    [5]
    5. Apparatus according to claim 4,
    wherein the memory device further comprises an input / output (I / O) circuit configured to interface with the SOC via the link and write data and read data from the plurality of memory cells; and where the memory device is configured to update a subset of the selected memory cells according to the PAR mask register without the I / O circuit receiving SOC update (REF) commands when the memory device is in mode auto-update and a partial array auto-update (PASR) is enabled and the memory device is configured to update the subset of the selected memory cells according to the PAR mask register on the I / O circuit that receives the SOC REF command when the memory device is in automatic update mode and PAAR is enabled.
    [6]
    Apparatus according to claim 5, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a bank segment and indicating whether an update is enabled or disabled for the corresponding segment, and where, when the memory device is in automatic update mode, PAAR is enabled and the REF command is a bank update command, the memory device is configured to ignore the update of each segment of a current bank whose corresponding segment mask bit indicates that the update is disabled.
    [7]
    Apparatus according to claim 5, wherein the plurality of memory cells is partitioned into a plurality of banks, wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether an update is enabled or disabled for the corresponding bank, and where, when the memory device is in automatic update mode, PAAR is enabled and the REF command is an update command per bank, the memory device is configured to ignore the update of a current bank when the corresponding bank mask bit indicates that the update is disabled.
    [8]
    Apparatus according to claim 5, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a bank segment and indicating whether an update is enabled or disabled for the corresponding segment and where, when the memory device is in automatic update mode, PAAR is enabled and the REF command is an update command for all banks, the memory device is configured to, for each bank, ignore the update of each segment of that bank whose corresponding segment mask bit indicates that the update is disabled.
    [9]
    Apparatus according to claim 5, wherein the plurality of memory cells is partitioned into a plurality of banks, wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether an update is enabled or disabled for the corresponding bank and where, when the memory device is in automatic update mode, PAAR is enabled and the REF command is an update command for all banks , the memory device is configured to ignore the update of each bank whose bit of the corresponding bank mask indicates that the update is disabled.
    [10]
    Apparatus according to claim 5, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register includes a plurality of mask bits bank and a plurality of segment mask bits, each bank mask bit corresponding to a bank and indicating whether an update is enabled or disabled for the corresponding bank, and each segment mask bit corresponding to a segment and indicating whether a update is enabled or disabled for the corresponding segment and where when the memory device is in auto update mode and PASR is enabled, the memory device is configured to ignore update for each bank whose corresponding bank mask bit indicates that the update is disabled for that bank and for each bank whose corresponding bank mask bit indicates that the update o is enabled for that bank, ignore the update of each segment of that bank whose corresponding segment mask bit indicates that the update is disabled.
    [11]
    11. Apparatus, comprising: a system on the chip (SOC) and a memory device configured to communicate over a link, where the SOC is configured to provide commands to the memory device via the link, where the memory device comprises: a plurality of memory cells; and a partial array update mask (PAR) register, where the memory device is configured to be in auto update mode or auto update mode, where the memory device is configured to update a subset of cells selected according to the PAR mask register without receiving SOC update commands (REF) when the memory device is in auto update mode and a partial matrix auto update (PASR) is enabled, and in which the device memory is configured to update the subset of the selected memory cells according to the PAR mask register that receives the SOC REF command when the memory device is in automatic update mode and an automatic partial matrix update (PAAR) is enabled.
    [12]
    Apparatus according to claim 11, wherein the memory device comprises a plurality of registers (MR) configured to implement a PAR enable register and the PAR mask register, the PAR enable register comprising a plurality of bits enable, including a PASR enable bit and a PAAR enable bit, the PASR enable bit when set, indicating that PASR is enabled, and the PAAR enable bit when set, indicating that PAAR is enabled.
    [13]
    13. Apparatus according to claim 12, in which the SOC is configured for each mode register used to implement the PAR enable register, issues a mode register write (MRW) command with a mode value corresponding to the memory device to set the PAAR enable bit of the PAR enable register, and for each mode register used to implement the PAR mask register, issue the MRW command with the mode value corresponding to the memory device, in order to have a mask value written to the PAR mask register, the mask value indicating an ignored update region comprising one or more portions of the plurality of memory cells that do not require updating.
    [14]
    14. Apparatus according to claim 13, in which the SOC is configured to receive the ignored update region of a memory driver from a computing system and issue MRW commands to set the PAAR enable bit of the data register enable PAR and set the mask value indicating the ignored update region after receiving the ignored update region from the memory driver.
    [15]
    Apparatus according to claim 13, wherein the SOC is configured to adjust a duration between the issuing of REF commands to the memory device based on the ignored update region.
    [16]
    Apparatus according to claim 11, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a bank segment and indicating whether an update is enabled or disabled for the corresponding segment and where when the memory device is in automatic update mode, the automatic update of the partial matrix is enabled and the REF command is an update command per bank, the memory device is configured to ignore the update of each segment of a current bank whose corresponding segment mask bit indicates that the update is disabled.
    [17]
    Apparatus according to claim 11, wherein the plurality of memory cells is partitioned into a plurality of banks, wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether an update is enabled or disabled for the corresponding bank, and when the memory device is in automatic update mode, automatic partial matrix update is enabled and the REF command is an update command per bank , the memory device is configured to ignore the update of a current bank when the corresponding bank mask bit indicates that the update is disabled.
    [18]
    Apparatus according to claim 11, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a segment of a bank and indicating whether an update is enabled or disabled for the corresponding segment and where, when the memory device is in automatic update mode, PAAR is enabled and the REF command is an update command for all banks,
    the memory device is configured to, each bank ignore the update of each segment of that bank whose corresponding segment mask bit indicates that the update is disabled.
    [19]
    An apparatus according to claim 11, wherein the plurality of memory cells is partitioned into a plurality of banks, wherein the PAR mask register comprises a plurality of bank mask bits, each bank mask bit corresponding to a bank and indicating whether an update is enabled or disabled for the corresponding bank and, when the memory device is in automatic update mode, PAAR is enabled and the REF command is an update command for all banks, the memory device is configured to ignore the update of each bank whose corresponding bank mask bit indicates that the update is disabled.
    [20]
    20. Apparatus according to claim 11, wherein the apparatus is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a navigation device communication, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop, a server and a device in an automotive vehicle.
    [21]
    21. Method for reducing memory energy consumption on a computer system device,
    where the device comprises a system on the chip (SOC) and a memory device configured to communicate with each other over a link, where the SOC is configured to provide commands to the memory device via the link, where the memory device comprises: a plurality of memory cells; and a plurality of mode (MR) registers configured to implement a partial array update enable (PAR) register and a PAR mask register, the PAR enable register comprising a plurality of enable bits, including a partial matrix auto update enable (PASR) and an automatic partial matrix update enable (PAAR) bit, the PASR enable bit when set, indicating that PASR is enabled, and the PAAR enable bit when set, indicating that PAAR is enabled and in which the method comprises: issuing, through the SOC, for each mode register used to implement the PAR enabling register, a mode register write command (MRW) with a mode value corresponding to the memory device to set the PAAR enable bit of the PAR enable register; issue, by SOC, for each mode register used to implement the PAR mask register, a mode register write command (MRW) with a mode value corresponding to the memory device to cause a mask value to be written in the PAR mask register, the mask value corresponding to an ignored update region; issue, via SOC, a REF command to the memory device; and ignore, by the memory device, update of the ignored update region based on the PAR mask register when the REF command is issued by the SOC and the PAAR enable bit is set.
    [22]
    22. The method of claim 21, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a bank segment and indicating whether an update is enabled or disabled for the corresponding segment and where the update jump comprises skipping the update of each segment of a current bank whose mask bit corresponding segment indicates that the update is disabled when the REF command is a bank update command and the PAAR enable bit is set.
    [23]
    23. The method of claim 21, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a segment of a bank and indicating whether an update is enabled or disabled for the corresponding segment and in which the update step comprises, for each bank, the update of each segment of that bank whose corresponding segment mask bit indicates that the update is disabled when the REF command is an update command for all banks and the PAAR enable bit is set.
    [24]
    24. Apparatus, comprising: a system on the chip (SOC) and a memory device configured to communicate over a link, where the SOC is configured to provide commands to the memory device via the link, where the memory device comprises: a plurality of memory cells; a partial matrix update mask register (PAR); and means for updating, where the memory device is configured to be in auto update mode or in automatic update mode, where the means for updating updates a subset of the memory cells selected according to the PAR mask register without receive update commands (REF) from SOC when the memory device is in auto update mode and a partial matrix auto update (PASR) is enabled and the means to update updates the subset of the selected memory cells according to the PAR mask register when receiving the SOC REF command when the memory device is in automatic update mode and an automatic partial matrix update (PAAR) is enabled.
    [25]
    Apparatus according to claim 24, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a bank segment and indicating whether an update is enabled or disabled for the corresponding segment and where, when the memory device is in automatic update mode, the PAAR enable bit is defined and the REF command is an update command per bank, the means to update ignore the update of each segment of a current bank whose corresponding segment mask bit indicates that the update is disabled.
    [26]
    26. The apparatus of claim 24, wherein the plurality of memory cells is partitioned into a plurality of banks, each bank comprising a plurality of segments, wherein the PAR mask register comprises a plurality of mask bits segment, each segment mask bit corresponding to a bank segment and indicating whether an update is enabled or disabled for the corresponding segment and where, when the memory device is in automatic update mode, the enable
    PAAR is defined and the REF command is an update command for all banks, the means to update, for each bank, ignore the update of each segment of that bank whose corresponding segment mask bit indicates that the update is disabled.
    类似技术:
    公开号 | 公开日 | 专利标题
    BR112020001854A2|2020-07-28|partial upgrade technique to save memory upgrade energy
    US9761298B2|2017-09-12|Method, apparatus and system for responding to a row hammer event
    US10600470B2|2020-03-24|Memory device and memory system performing a hammer refresh operation and associated operations
    Bhati et al.2015|DRAM refresh mechanisms, penalties, and trade-offs
    US9772803B2|2017-09-26|Semiconductor memory device and memory system
    JP2016523411A|2016-08-08|Hybrid memory device
    TWI695267B|2020-06-01|Memory system, memory module and operation method thereof
    KR100816053B1|2008-03-21|Memory device, memory system and dual port memory device with self-copy function
    KR20050018046A|2005-02-23|Memory controller for changing a frequency of memory clock signal selectively and method of controlling read operation of the memory using the same
    US6931479B2|2005-08-16|Method and apparatus for multi-functional inputs of a memory device
    US20150127890A1|2015-05-07|Memory module with a dual-port buffer
    KR101204645B1|2012-11-23|Memory throughput increase via fine granularity of precharge management
    KR20160094767A|2016-08-10|Memory device and method for implementing information transmission using idle cycles
    KR102078562B1|2020-02-18|Refresh address generator and volatile memory device comprising thereof
    KR100963702B1|2010-06-14|System and method for decoding commands based on command signals and operating state
    US20090182977A1|2009-07-16|Cascaded memory arrangement
    US10559335B2|2020-02-11|Method of training drive strength, ODT of memory device, computing system performing the same and system-on-chip performing the same
    US9934154B2|2018-04-03|Electronic system with memory management mechanism and method of operation thereof
    US11195568B1|2021-12-07|Methods and systems for controlling refresh operations of a memory device
    BR112020005308A2|2020-09-24|robust write trigger scheme for static random access memory compilers
    US8909878B2|2014-12-09|Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel
    JP2012221534A|2012-11-12|Semiconductor storage device and method for refreshing semiconductor storage device
    同族专利:
    公开号 | 公开日
    CN110945589A|2020-03-31|
    WO2019027544A1|2019-02-07|
    US20200321051A1|2020-10-08|
    US11164618B2|2021-11-02|
    TW201923764A|2019-06-16|
    US10332582B2|2019-06-25|
    US20210343331A1|2021-11-04|
    US20190221252A1|2019-07-18|
    TWI691958B|2020-04-21|
    US20190043558A1|2019-02-07|
    EP3662475A1|2020-06-10|
    US10726904B2|2020-07-28|
    SG11201912352RA|2020-02-27|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    JP2001338489A|2000-05-24|2001-12-07|Mitsubishi Electric Corp|Semiconductor device|
    JP2002064150A|2000-06-05|2002-02-28|Mitsubishi Electric Corp|Semiconductor device|
    JP5034149B2|2000-10-05|2012-09-26|富士通セミコンダクター株式会社|Semiconductor memory and control method thereof|
    US6590822B2|2001-05-07|2003-07-08|Samsung Electronics Co., Ltd.|System and method for performing partial array self-refresh operation in a semiconductor memory device|
    JP2002373489A|2001-06-15|2002-12-26|Mitsubishi Electric Corp|Semiconductor memory|
    KR100437610B1|2001-09-20|2004-06-30|주식회사 하이닉스반도체|A low power semiconductor memory device with normal mode and partial array self refresh mode|
    US6738861B2|2001-09-20|2004-05-18|Intel Corporation|System and method for managing data in memory for reducing power consumption|
    DE10154770B4|2001-11-08|2004-11-18|Infineon Technologies Ag|Dynamic memory device with a selection device for the selective fading out of unused memory cells during the refresh|
    US6650587B2|2001-11-19|2003-11-18|Micron Technology, Inc.|Partial array self-refresh|
    US6618314B1|2002-03-04|2003-09-09|Cypress Semiconductor Corp.|Method and architecture for reducing the power consumption for memory devices in refresh operations|
    US7043599B1|2002-06-20|2006-05-09|Rambus Inc.|Dynamic memory supporting simultaneous refresh and data-access transactions|
    US6920523B2|2002-10-07|2005-07-19|Infineon Technologies Ag|Bank address mapping according to bank retention time in dynamic random access memories|
    JP4205396B2|2002-10-30|2009-01-07|エルピーダメモリ株式会社|Semiconductor integrated circuit device|
    JP2004273029A|2003-03-10|2004-09-30|Sony Corp|Storage device, and refreshing control circuit and refreshing method used for same|
    US6912168B2|2003-03-18|2005-06-28|United Memories, Inc.|Non-contiguous masked refresh for an integrated circuit memory|
    KR100605606B1|2003-05-29|2006-07-28|주식회사 하이닉스반도체|Synchronous self refresh exit control method and circuit in memory device|
    US6956782B2|2003-09-30|2005-10-18|Infineon Technologies Ag|Selective bank refresh|
    KR100621619B1|2003-11-14|2006-09-13|삼성전자주식회사|Semiconductor memory device for performing refresh operation|
    US7345940B2|2003-11-18|2008-03-18|Infineon Technologies Ag|Method and circuit configuration for refreshing data in a semiconductor memory|
    KR100653688B1|2004-04-29|2006-12-04|삼성전자주식회사|Semiconductor memory device and refresh method of the same, and memory system for the same|
    KR100611774B1|2004-06-03|2006-08-10|주식회사 하이닉스반도체|Bank based partial array self refresh apparatus in semiconductor memory device and its method|
    KR20060084071A|2005-01-17|2006-07-24|삼성전자주식회사|Refresh control circuits for use in semiconductor memory and method for control therefore|
    US7702839B2|2005-04-12|2010-04-20|Nokia Corporation|Memory interface for volatile and non-volatile memory devices|
    US7492656B2|2006-04-28|2009-02-17|Mosaid Technologies Incorporated|Dynamic random access memory with fully independent partial array refresh function|
    JP2008065971A|2006-08-10|2008-03-21|Fujitsu Ltd|Semiconductor memory and memory system|
    JP4299849B2|2006-08-22|2009-07-22|エルピーダメモリ株式会社|Semiconductor memory device and refresh control method thereof|
    JP2008084426A|2006-09-27|2008-04-10|Fujitsu Ltd|Semiconductor memory and system|
    KR101193348B1|2006-12-22|2012-10-19|싸이던스 코포레이션|Mask programmable anti-fuse architecture|
    JP5098391B2|2007-03-28|2012-12-12|富士通セミコンダクター株式会社|Semiconductor memory, system, and operation method of semiconductor memory|
    US9071246B2|2007-09-14|2015-06-30|Agate Logic, Inc.|Memory controller for heterogeneous configurable integrated circuits|
    KR100899394B1|2007-10-31|2009-05-27|주식회사 하이닉스반도체|Refresh controlling circuit|
    US7983108B2|2008-08-04|2011-07-19|Micron Technology, Inc.|Row mask addressing|
    US8762656B2|2008-12-30|2014-06-24|Micron Technology, Inc.|Temperature alert and low rate refresh for a non-volatile memory|
    JP5599977B2|2009-01-22|2014-10-01|ピーエスフォールクスコエスエイアールエル|Semiconductor memory device|
    JP2011034632A|2009-07-31|2011-02-17|Elpida Memory Inc|Semiconductor memory device and method of testing the same|
    US20110296098A1|2010-06-01|2011-12-01|Dell Products L.P.|System and Method for Reducing Power Consumption of Memory|
    JP2012033228A|2010-07-30|2012-02-16|Elpida Memory Inc|Semiconductor device and method for controlling the same|
    US9292426B2|2010-09-24|2016-03-22|Intel Corporation|Fast exit from DRAM self-refresh|
    US8705302B2|2010-09-24|2014-04-22|Samsung Electronics Co., Ltd.|Semiconductor memory devices having self-refresh capability|
    US20130100755A1|2011-10-21|2013-04-25|Samsung Electronics Co., Ltd.|Semiconductor memory device implementing comprehensive partial array self refresh scheme|
    EP2620838B1|2012-01-26|2015-04-22|ST-Ericsson SA|Automatic partial array self-refresh|
    TWI503662B|2012-12-27|2015-10-11|Ind Tech Res Inst|Memory control device and method|
    US9383809B2|2013-11-13|2016-07-05|Qualcomm Incorporated|System and method for reducing memory I/O power via data masking|
    JP6425462B2|2014-08-27|2018-11-21|ルネサスエレクトロニクス株式会社|Semiconductor device|
    US9418723B2|2014-12-23|2016-08-16|Intel Corporation|Techniques to reduce memory cell refreshes for a memory device|
    WO2016126264A1|2015-02-06|2016-08-11|Hewlett Packard Enterprise Development Lp|Refreshing an identified partial array|
    US9607677B2|2015-03-31|2017-03-28|Micron Technology, Inc.|Apparatuses for resetting an address counter during refresh operations|
    US9824742B1|2016-04-28|2017-11-21|Qualcomm Incorporated|DRAM access in self-refresh state|
    KR20170131127A|2016-05-20|2017-11-29|삼성전자주식회사|Memory device shared by two or more processors and su|ystem incluing the same|
    US10332582B2|2017-08-02|2019-06-25|Qualcomm Incorporated|Partial refresh technique to save memory refresh power|US10332582B2|2017-08-02|2019-06-25|Qualcomm Incorporated|Partial refresh technique to save memory refresh power|
    US20190378564A1|2018-06-11|2019-12-12|Nanya Technology Corporation|Memory device and operating method thereof|
    US11152050B2|2018-06-19|2021-10-19|Micron Technology, Inc.|Apparatuses and methods for multiple row hammer refresh address sequences|
    US10573370B2|2018-07-02|2020-02-25|Micron Technology, Inc.|Apparatus and methods for triggering row hammer address sampling|
    US10685696B2|2018-10-31|2020-06-16|Micron Technology, Inc.|Apparatuses and methods for access based refresh timing|
    CN113168861A|2018-12-03|2021-07-23|美光科技公司|Semiconductor device for performing row hammer refresh operation|
    CN111354393A|2018-12-21|2020-06-30|美光科技公司|Apparatus and method for timing interleaving for targeted refresh operations|
    US10957377B2|2018-12-26|2021-03-23|Micron Technology, Inc.|Apparatuses and methods for distributed targeted refresh operations|
    US10770127B2|2019-02-06|2020-09-08|Micron Technology, Inc.|Apparatuses and methods for managing row access counts|
    GB2578932B|2019-02-14|2021-02-24|Imagination Tech Ltd|Allocation of memory|
    US11043254B2|2019-03-19|2021-06-22|Micron Technology, Inc.|Semiconductor device having cam that stores address signals|
    US11227649B2|2019-04-04|2022-01-18|Micron Technology, Inc.|Apparatuses and methods for staggered timing of targeted refresh operations|
    US11264096B2|2019-05-14|2022-03-01|Micron Technology, Inc.|Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits|
    US11158364B2|2019-05-31|2021-10-26|Micron Technology, Inc.|Apparatuses and methods for tracking victim rows|
    US11158373B2|2019-06-11|2021-10-26|Micron Technology, Inc.|Apparatuses, systems, and methods for determining extremum numerical values|
    US11139015B2|2019-07-01|2021-10-05|Micron Technology, Inc.|Apparatuses and methods for monitoring word line accesses|
    US11200942B2|2019-08-23|2021-12-14|Micron Technology, Inc.|Apparatuses and methods for lossy row access counting|
    US20210064119A1|2019-08-26|2021-03-04|Micron Technology, Inc.|Bank configurable power modes|
    US11222682B1|2020-08-31|2022-01-11|Micron Technology, Inc.|Apparatuses and methods for providing refresh addresses|
    US11222686B1|2020-11-12|2022-01-11|Micron Technology, Inc.|Apparatuses and methods for controlling refresh timing|
    US11264079B1|2020-12-18|2022-03-01|Micron Technology, Inc.|Apparatuses and methods for row hammer based cache lockdown|
    法律状态:
    2021-11-03| B350| Update of information on the portal [chapter 15.35 patent gazette]|
    优先权:
    申请号 | 申请日 | 专利标题
    US15/667,618|US10332582B2|2017-08-02|2017-08-02|Partial refresh technique to save memory refresh power|
    US15/667,618|2017-08-02|
    PCT/US2018/034659|WO2019027544A1|2017-08-02|2018-05-25|Partial refresh technique to save memory refresh power|
    [返回顶部]